| CONFERENCE PROGRAMME | ||||||||||||
| Sunday, Jan 3, 2016 | ||||||||||||
| 18:00-20:00 | Registration Art Gallery |
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| Monday, Jan 4, 2016 | ||||||||||||
| 8:00-9:00 | Registration Art Gallery |
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| 9:00-9:30 | INAUGURAL SESSION Pala Ballroom Chief Guest: Prof. Partha P. Chakrabarti |
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| 9:30-10:10 | Visionary Talk: Driving unconventional growth through industrial internet of things. Dr. Prithviraj Banerjee, CTO & Executive VP, Schneider Electric Pala Ballroom Chair: Prof. Bhargab B. Bhattacharya |
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| 10:10-10:50 | Keynote: Smartphone Chipset Design for an inclusive World Venugopal Puvvada, VP, Engineering, Qualcomm Pala Ballroom Chair: Prof. Niraj K. Jha |
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| 10:50-11:20 | Tea Break Foyer-II |
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| 11:20-13:00 | Session M/A-1: Process Technologies and Advances in Memories Conference Room 4 Chair: Dr Devesh Dwivedi |
Session M/B-1: Network on Chip Pala-I Chair: Prof. Bhabani P. Sinha |
Session M/C-1: Power Aware Design Pala-II Chair: Prof. Partha Pratim Pande |
Special Session M/D-1: Design of Microfluidic Biochips: Connecting Algorithms and Foundations of Chip Design to Biochemistry and the Life Sciences Pala-III Chair: Prof. Suman Chakraborty |
Session M/E-1 Foyer-I Chairs: Chitra Hariharan, Anuradha Srinivasan |
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| 11:20-11:40 | M/A-1.1 | A Novel Co-Design Methodology for Optimizing ESD Protection Device using Layout Level Approach. | M/B-1.1 | Hierarchical Cluster based NoC design using Wireless Interconnects for Coherence Support. | M/C-1.1 | Accurate and efficient Estimation of Dynamic Virtual Ground Voltage in Power Gated Circuits. | M/D-1.1 | The Coming of Age of Microfluidics: EDA Solutions for Enabling Biochemistry on a Chip | Industry Forum I | |||
| M/E-1.1 | Future Trends in Automotive Industry | |||||||||||
| Vishnuram Abhinav, Dheeraj Kumar Sinha, Amitabh Chatterjee, Forrest Brewer | Tanya Shreedhar, Sujay Deb | Lokesh Garg, Vineet Sahula | Prof. Tsung-Yi Ho | Vinay Shenoy, Infineon | ||||||||
| 11:40-12:00 | M/A-1.2 | FinFET Device Circuit Co-design Issues: Impact of Circuit Parameters on Delay. | M/B-1.2 | A Power Efficient Dual Link Mesh NoC Architecture to Support Non-uniform Traffic Arbitration at Routing Logic. | M/C-1.2 | Applying River Formation Dynamics to Analyze VLSI Power Grid Networks. | M/D-1.2 | Pin-Count Reduction Techniques for Logic Integrated Digital Microfluidic Biochips | M/E-1.2 | Emergence of Intelligence Age | ||
| Archana Pandey, Harsh Kumar, Pranshu Goyal, Sudeb Dasgupta, Sanjeev Kumar Manhas, Anand Bulusu | Sonal Yadav, Vijay Laxmi, Manoj Singh Gaur | Satyabrata Dash, Krishna Lal Baishnab, Gaurav Trivedi | Swapna Gupta, Qualcomm Ventures | |||||||||
| 12:00-12:20 | M/A-1.3 | Analytical Modeling of Dual Material Gate All Around Stack Architecture of Tunnel FET. | M/B-1.3 | A Statistical Model for Hybrid Wireless Network on Chip. | M/C-1.3 | Energy-Aware Memory Mapping for Hybrid FRAM-SRAM MCUs in IoT Edge Devices. | Prof. Shigeru Yamashita | M/E-1.3 | A Shorter Design Cycle for 3GHz CPU Design | |||
| Dr.N.B. Balamurugan, Mr.S. Manikandan, Ms.G. Srimathi, Lakshmi Priya.G | Priyanka Mitra | Hrishikesh Jayakumar, Arnab Raha, Vijay Raghunathan | M/D-1.3 | Correctness Checking of Bio-chemical Protocol Realizations on a Digital Microfluidic Biochip | Raghu Kodali, ARM | |||||||
| 12:20-12:40 | M/A-1.4 | Fast FinFET Device Simulation Under Process-voltage Variations Using an Assisted Speed-up Mechanism. | M/B-1.4 | Energy Efficient and Congestion-Aware Router Design for Future NoCs. | M/C-1.4 | A Methodology for Thermal Characterization Abstraction of Integrated Opto-Electronic Layouts. | M/E-1.4 | Small cells: Enabling Secure, Fail-Proof and Universal Communication | ||||
| Sourindra Chaudhuri, Ajay Bhoj, Debajit Bhattcharya, Niraj Jha | Wazir Sing, Sujay Deb | Lawrence Schlitt, Priyank Kalla, Steve Blair | Dr. Ansuman Banerjee | Aravind Ganesan, SignalChip | ||||||||
| 12:40-13:00 | M/A-1.5 | Circuit and Architectural Co-Design for Reliable Adder Cells with Steep Slope Tunnel Transistors for Energy Efficient Computing. | M/B-1.5 | SPECTRA: A Framework for Thermal Reliability Management in Silicon-Photonic Networks-on-Chip. | M/C-1.5 | An Energy Efficient Dynamically Reconfigurable QR Decomposition for Wireless MIMO Communication. | M/D-1.4 | Computer-Aided-Design (CAD) for Fluidic Sample Preparation using Digital Microfluidic Biochips | M/E-1.5 | Security of Things-Lessons for the connected future | ||
| Sadulla Shaik, Ramesh Vaddi, Sri Rama Krishna K | Sai Vineel Reddy Chittamuru, Sudeep Pasricha | Ashish Pradhan, S K Nandy | Dr. Sudip Roy | SenthilVelu/Prajit Nandi, SankalpSemi | ||||||||
| 13:00-14:00 | LUNCH Sunderbans |
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| 14:00-14:40 | Visionary Talk: FinFETs: Quo Vadis? Prof. Niraj K. Jha, Princeton University Pala Ballroom Chair: Prof. Yao-Wen Chang |
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| 14:50-15:50 | PANEL DISCUSSION: Technology, Market, Policy – drivers for a smarter infrastructure in a connected and inclusive world. Panelists: Talleen Kumar (Principal Secretary – IT, GoWB), Vinay Shenoy (MD, Infineon India and Chairman, IESA), Angshik Chaudhuri (Cisco), Shivoo Koteshwar (Mediatek India), Pradip K. Dutta (VP & MD, Synopsys India) [Moderator] Pala Ballroom |
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| 15:50-16:20 | Tea Break Foyer-II |
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| 16:20-17:20 | Session M/A-2: Analog / RF Design-1 Foyer-I Chair: Prof. Amit Patra |
Session M/B-2: Advances in Architecture Pala-I Chair: Dr. C. Rama Mohan |
Session M/C-2: FPGA based Designs and Reconfigurable Architectures Pala-II Chair: Prof. Anupam Chattopadhyay |
Special Session M/D-2: The Future of NoCs: New Technologies and Architectures Pala-III Chair: Prof. Manoj Singh Gaur |
Session M/E-2 Conference Room 4 Chair: Dr. Soumya Pandit, Dr. Sayantan Das |
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| 16:20-16:40 | M/A-2.1 | A Gyrator based Output Resistance Enhancement Scheme for a Differential Amplifier. | M/B-2.1 | Massed Refresh: An Energy-Efficient Technique to Reduce Refresh Overhead in Hybrid Memory Cube Architectures. | M/C-2.1 | Error Resilient Secure Multi-Gigabit Optical Link Design for High Energy Physics Experiment. | M/D-2.1 | Millimeter (mm)-Wave Wireless NoC as Interconnection Backbone for Multicore Chips: Promises and Challenges | PhD Forum
Click here for Details |
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| Prajwal M. V, Srinivas B. S, Shodhan S, Jayaram Reddy M. K, Tonse Laxminidhi | Ishan Thakkar, Sudeep Pasricha | Jubin Mitra, Shuaib Ahmad Khan, Rourab Paul, Sanjoy Mukherjee, Amlan Chakrabarti, Tapan Kumar Nayak | ||||||||||
| 16:40-17:00 | M/A-2.2 | A Stacked VCO Architecture for Generating Multi-Level Synchronous Control Signals. | M/B-2.2 | Towards a Better Cache Utilization by Selective Data Storage for CMP Last Level Caches. | M/C-2.2 | Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs. | Prof. Partha Pratim Pande | |||||
| Samiran Dam, Pradip Mandal | Shirshendu Das, Hemangee K. Kapoor | Ayan Palchaudhuri, Anindya Sundar Dhar | ||||||||||
| 17:00-17:20 | M/A-2.3 | A Fully-Integrated Radio-Frequency Power Amplifier in 28nm CMOS Technology mounted in BGA Package. | M/B-2.3 | Achieving Efficient QR Factorization by Algorithm-Architecture Co-Design of Householder Transformation. | M/C-2.3 | A High Throughput Non-uniformly Quantized Binary SOVA Detector on FPGA. | M/D-2.2 | Illuminating the Future of Multicore Computing with Silicon Nanophotonic NoCs | ||||
| Ankur Gupta, Mayank Shrivastava, Maryam Shojaei Baghini, Harald Gossner, V. Ramgopal Rao | Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S K Nandy, Ranjani Narayan | Saugata Datta, Kuruvilla Varghese, Shayan Srinivasa | ||||||||||
| 17:20-18:20 | 17:20-17:40 | M/A-2.4 | Power Optimization Of LNA For LTE Receiver. | Session M/BI: Embedded Invited Presentation Neuromorphic Computing Enabled by Spin-Transfer Torque Devices Kaushik Roy et. al. Chair: Dr. C. Rama Mohan |
M/C-2.4 | An Improved Design of a Reversible Fault Tolerant LUT-Based FPGA. | Dr. Sudeep Pasricha | |||||
| Vinaya MM, Roy Paily, Anil Mahanta | Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md Hasan Babu | |||||||||||
| 17:40-18:00 | M/A-2.5 | A Wide-band Receiver Front-end With Programmable Frequency Selective Input Matching. | M/C-2.5 | A Modified Hill Climbing Based Watershed Algorithm and Its Real Time FPGA Implementation. | M/D-2.3 | Inductive-Coupling 3D Wireless NoC Designs | Design Contest Sponsored by Cadence |
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| Manas Lenka, Akash Agrawal, Vishal Khatri, Gaurab Banerjee | Pradipta Roy, Prabir Kumar Biswas, Binoy Kumar Das | Dr. Hiroki Matsutani | ||||||||||
| 18:00-18:20 | M/C-2.6 | An Efficient Hardware Implementation of Canny Edge Detection Algorithm. | ||||||||||
| Sangeetha D, Deepa P | ||||||||||||
| 18:00-19:00 | High Tea Sunderbans |
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| 19:00-20:00 | Cultural Program Pala Ballroom |
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| Tuesday, Jan 5, 2016 | ||||||||||||
| 8:00-9:00 | Registration Art Gallery |
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| 9:00-9:40 | Visionary Talk: BlueDBM: A multi-access distributed flash store for big data analytics Prof. Arvind, MIT Pala Ballroom Chair: Prof. Susmita Sur-Kolay |
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| 9:40-10:20 | Keynote: Energy Efficient & Secure Computing in Nanoscale CMOS Dr. Vivek De, Intel Fellow & Director, Circuit Technology Research, Intel Labs Pala Ballroom Chair: Prof. Susmita Sur-Kolay |
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| 10:20-10:50 | Tea Break Foyer-II |
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| 10:50-13:00 | Session T/A-1: High Performance Analog for Digital Systems Pala-I Chair: Prof. Susanta Sen |
Session T/B-1: Advances in Timing, Verification and Synthesis Pala-II Chair: Prof. Sharad Seth |
Session T/C-1: Advances in Digital Design Conference Room 4 Chair: Sabyasachi De |
Special Session T/D-1: New Directions in Hardware Security Pala-III Chair: Prof. Debdeep Mukhopadhyay |
Session T/E-1 Foyer-I Chair: TBD |
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| 10:50-11:10 | T/A-1.1 | A 1-tap 10.3125Gb/s Programmable Voltage Mode Driver in 28nm CMOS Technology. | T/B-1.1 | Sharing and Re-Use of Statistical Timing Macro-models across Multiple Voltage Domains. | T/C-1.1 | Logic Synthesis in Reversible PLA. | T/D-1.1 | A Novel Modeling Attack on Lightweight Secure PUF | Industry Forum II | |||
| Raghavendra R G, Balbeer Singh Rathor | Debjit Sinha, Vladimir Zolotov, Eric Fluhr, Michael H. Wood, Jeffrey Ritzinger, Natesan Venkateswaran, Stephen Shuma | Nazma Tara, Nawshi Matin, Hafiz Md Hasan Babu | T/E-1.1.1 | Navigating the perfect storm-Latest trends in SoC verification | ||||||||
| 11:10-11:30 | T/A-1.2 | -1.1V to +1.1V 3:1 Power Switch Architecture for Controlling Body Bias of SRAM Array in 28nm UTBB CMOS FDSOI. | T/B-1.2 | ChADD: An ADD based Chisel Compiler with reduced Syntactic Variance. | T/C-1.2 | Early Scenario Pruning for Efficient Design Space Exploration in Physical Synthesis. | Pradeep Salla, Mentor Graphics | |||||
| Amit Chhabra, Vikas Rana | Vikas Chauhan, Neel Gala, Kamakoti V | Mohd Anwar, Sourav Saha, Matthew Ziegler, Lakshmi Reddy | Dr. Rajat Subhra Chakraborty | T/E-1.1.2 | Streamlined Development of Complex ASICs/FPGAs | |||||||
| 11:30-11:50 | T/A-1.3 | A New Sense Amplifier Topology with Improved Performance for High Speed SRAM Applications | T/B-1.3 | An Efficient Method for Clock Skew Scheduling to reduce Peak Current. | T/C-1.3 | A Modified SRAM BASED Low Power Memory Design. | Paritosh Joshi, Infinera | |||||
| T/D-1.2 | Towards Trust Validation of Hardware Intellectual Property (IP) Cores | T/E-1.1.3 | Growing challenges of ever increasing smarter and connected devices – A sneak peak into Intel’s IOT platform solution with end-to-end coverage. | |||||||||
| Anil G Kumar, Mohammad Hashmi | Arunkumar Vijayakumar, Vinay Patil, Sandip Kundu | Apoorva Pathak, Harish Peta, Divyesh Sachan, Manish Goswami | Shridhar G Bendi, Intel | |||||||||
| 11:50-12:10 | T/A-1.4 | A 0.5V Vmin 6T SRAM in 28nm UTBB FDSOI Technology Using Compensated WLUD Scheme with Zero Performance Loss. | T/B-1.4 | Path Based Timing Validation for Timed Asynchronous Design. | T/C-1.4 | Stochastic Number Generation with Few Inputs. | User / Designer Track Presentations I [11:50-12:50] |
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| Dr. Prabhat Mishra | T/E-1.2.1 | A Formal Method to Uncover Sequential Redundancy in an Industrial Context Pradeep Kumar Nalla, RajKumar Gajavelly, Ashutosh Misra and Hari Mony | ||||||||||
| Ashish Kumar, G.S. Visweswaran, Vinay Kumar, Kaushik Saha | William Lee, Tannu Sharma, Kenneth S. Stevens | Ritsuko Muguruma, Shigeru Yamashita | T/E-1.2.2 | Accelerating SOC Verification Closure using Property Synthesis Technology | ||||||||
| 12:10-12:30 | T/A-1.5 | A quarter-rate 2^7-1 pseudo-random binary sequence generator using interleaved architecture. | T/B-1.5 | Symptomatic bug localization for functional debug of hardware designs. | T/C-1.5 | Exploring Approximate Computing for Yield Improvement via Re-design of Adders for Error-resilient Applications. | T/D-1.3 | Security and Internet of Things (IoT) | Rejoyce Ponnattil Jacob, Jasmin Rahiman, Ravindra Nibandhe and Anuj Kumar | |||
| Dr. Seetharam Narasimhan | T/E-1.2.3 | Exploiting Energy-scaling and Co-operation as power-management knobs for Video-Conferencing | ||||||||||
| Mahendra Sakare, Shalabh Gupta | Debjit Pal, Shobha Vasudevan | Sunil Dutt, Harsh Patel, Sukumar Nandi, Gaurav Trivedi | Binu Joseph, Arun Iyer, Ganesh Vijayan and Ansu Mathew | |||||||||
| 12:30-12:50 | T/A-1.6 | Characterization of a Novel Low Leakage Power and Area Efficient 7T SRAM Cell. | T/C-1.6 | An Efficient VLSI Architecture for Discrete Hadamard Transform. | T/E-1.2.4 | Identifying (Non)Resilient Portions of a Video Compression IP to exploit Energy-Quality trade-offs | ||||||
| Venkatareddy Ambati, sithara R, Nithin Kumar Y.B., Vasantha M.H | Noor Mahammad Sk, Mohamed Asan Basiri M | Arun Iyer, Navnish Kumar, Tushar shah and Sashank Kurella | ||||||||||
| 13:00-14:00 | LUNCH Sunderbans |
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| 14:00-16:00 | Session T/A-2: Analog/RF Circuits for Communications Pala-I Chair: Dr. Karthik Natarajan |
Session T/B-2: New Test Generation Methods Pala-II Chair: Dr. Tapan Chakraborty |
Session T/C-2: Technologies for Secure Embedded Circuits and Systems Pala-III Chair: Prof. Preeti R. Panda |
Session T/D-2: Emerging Technologies in Integrated Circuits and Healthcare Conference Room 4 Chair: Pradeep Salla |
Session T/E-2 Foyer-I Chair: TBD |
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| 14:00-14:20 | T/A-2.1 | A 1.5mA, 2.4GHz ZigBee/BLE QLMVF Front-End Receiver with Split TCAs in 180nm CMOS. | T/B-2.1 | TRAP: Test Generation Driven Classification of Analog/RF ICs Using Adaptive Probabilistic Clustering Algorithm. | T/C-2.1 | A Tiny Coprocessor for Elliptic Curve Cryptography over the 256-bit NIST Prime Field. | T/D-2.1 | Analysis, modeling, and applications of the straintronics devices for the future spin-based integrated circuits | Industry Forum III | |||
| T/E-2.1.1 | Enterprise Computing-Innovation through Collaboration is the way forward! | |||||||||||
| Sesha Sairam Regulagadda, Purushothama Chary, Rizwan Shaik Peerla, Mohd Abdul Naseeb, Amit Acharyya, Rajalakshmi P, Ashudeb Dutta | Sabyasachi Deyati, Abhijit Chatterjee, Barry Muldrey | Jeroen Bosmans, sujoy sinha roy, Kimmo Järvinen, Ingrid Verbauwhede | Mahmood Barangi, Pinaki Mazumder | Prasad Joshi, IBM | ||||||||
| 14:20-14:40 | T/A-2.2 | Wideband Active Delay Cell Design for Analog Domain Coherent DP-QPSK Optical Receiver | T/B-2.2 | Fault Modeling and Simulation of MEDA based Digital Microfluidics Biochips. | T/C-2.2 | A Practical Template Attack on MICKEY-128 2.0 Using PSO Generated IVs and LS-SVM. | T/D-2.2 | A Generic Implementation of Barriers using Optical Interconnects. | T/E-2.1.2 | Foundation IP challenges | ||
| Saurabh Anmadwar, Nandakumar Nambath, Shalabh Gupta | Vineeta Shukla, Noohul Basheer Zain Ali, Fawnizu Azmadi Hussin, Nor Hisham Hamid, Madiha Sheikh | Abhishek Chakraborty, Debdeep Mukhopadhyay | Sandeep Chandran, Eldhose Peter, Preeti Panda, Smruti R. Sarangi | Rituparna Mandal, MediaTek | ||||||||
| 14:40-15:00 | T/A-2.3 | A 0.8mW Peak Power Consumption, 24GHz (K-Band), Super-Regenerative Receiver with 200pJ/bit Energy Efficiency, for IoT. | T/B-2.3 | Thermal-Safe Schedule Generation For System-on-Chip Testing. | T/C-2.3 | Memristor based Arbiter PUF: Cryptanalysis Threat and its Mitigation. | T/D-2.3 | ILP-Based Synthesis for Sample Preparation Applications on Digital Microfluidic Biochips. | T/E-2.1.3 | Managing Storage Solutions in the Era of Data Explosion | ||
| Mihai Sanduleanu, Badreyya Al Shehhi | Rajit Karmakar, Santanu Chattopadhyay | Urbi Chatterjee, Rajat Subhra Chakraborty, Jimson Mathew, Dhiraj K. Pradhan | Abhimanyu Yadav, Trung Anh Dinh, Daiki Kitagawa, Shigeru Yamashita | Niranjan Pol, Seagate | ||||||||
| 15:00-15:20 | T/A-2.4 | An Efficient On Chip Power Management Architecture for Solar Energy Harvesting Systems. | Session T/BI: Embedded Tutorial: Database Search and ATPG-Interdisciplinary Domains and Algorithms Vishwani Agarwal et. al. |
T/C-2.4 | Security metrics for power based SCA resistant hardware implementation. | T/D-2.4 | Metal Carbon Nanotube Schottky Barrier Diode with Detection of Polar Non-Polar Gases. | User / Designer Track Presentations II [15:00-16:00] |
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| T/E-2.2.1 | Low Power Hybrid 1-bit Full Adder Circuit for Energy-Efficient Arithmetic Applications | |||||||||||
| Saroj Mondal, Roy Paily | Jungmin Park, Akhilesh Tyagi | Sarvesh Agarwal, Dr. Sanjeev Kumar Manhas, Dr.Sudeb Das Gupta, Dr.Neeraj Jain | Parameshwara M C and Srinivasaiah H C | |||||||||
| T/E-2.2.2 | Automated Power modelling solutions for Analog Mixed Signal (AMS) Designs | |||||||||||
| 15:20-15:40 | T/A-2.5 | A 14 bit Dual Channel Incremental Continuous-time Delta Sigma Modulator for Multiplexed Data Acquisition. | T/C-2.5 | Security Verification of 3rd Party Intellectual Property Cores for Information Leakage. | T/D-2.5 | Nanostructured Silicon Oxide Immunosensor Integrated with Noise Spectroscopy Electronics for POC Diagnostics. | Rechel Subhasini and Susmita Gupta | |||||
| T/E-2.2.3 | Variability Resilient, Low Energy Differential Current Compensation Based Sense Amplifier for Robust SRAM | |||||||||||
| Kamlesh Singh, Shanthi Pavan | Jeyavijayan Rajendran, Arunshankar Muruga Dhandayuthapany, Ramesh Karri, Vivekananda Vedula | Naren Das, Nirmalya Samanta, Chirasree Roychaudhuri | Bhupendra S Reniwal, Santosh Vishvakarma and Devesh Dwivedi | |||||||||
| 15:40-16:00 | T/A-2.6 | A 0.5-4GHz Programmable-Bandwidth Fractional-N PLL for Multi-protocol SERDES in 28nm CMOS. | T/E-2.2.4 | Design of all-optical division-by-two cum 1's complement conversion circuit | ||||||||
| Jayesh Wadekar, Biman Chattopadhyay, Ravi Mehta, Gopalkrishna Nayak | Tanay Chattopadhyay and Arunava Bhattachryya | |||||||||||
| 16:00-16:30 | Tea Break Foyer-II |
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| 16:30-17:30 | PANEL DISCUSSION: The Business Case for Women In Semiconductor Engineering (WISE) – Challenges and Opportunities. Panelists: Rituparna Mandal (Mediatek), Swapna Banerjee (IITKGP), Sumeet Agrawal (Intel), Swapna Gupta (Qualcomm Ventures), Pamela Kumar (CCICI) [Moderator] Pala Ballroom |
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| 17:30-18:00 | NETWORKING BREAK | |||||||||||
| 18:00-18:40 | AWARDS CEREMONY Sponsored by ARM Pala Ballroom |
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| 18:45-19:30 | Banquet Speech: Computational Thinking meets Design Thinking: Technology and Arts collaborations Prof. Erik Brunvand, University of Utah Pala Ballroom Chair: Prof. Krishnendu Chakrabarty |
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| 19:30 | Banquet Dinner Sunderbans |
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| Wednesday, Jan 6, 2016 | ||||||||||||
| 8:00-9:00 | Registration Art Gallery |
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| 9:00-9:40 | Plenary Lecture: Design for Manufacturability for sub-14 nanometer technologies Prof. Yao-Wen Chang, National Taiwan University Pala Ballroom Chair: Prof. Pallab Dasgupta |
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| 9:40-10:20 | Keynote: Test Strategies for Sub-20nm Designs Dr. Nilanjan Mukherjee, Mentor Graphics Corporation Pala Ballroom Chair: Prof. Pallab Dasgupta |
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| 10:20-10:50 | Tea Break Foyer-II |
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| 10:50-13:00 | Session W/A-1: Analog/RF Design-2 Pala-I Chair: Prof. Subhanshu Gupta |
Session W/B-1: Issues in Embedded System Design Pala-II Chair: Prof. Nikil Dutt |
Session W/C-1 Conference Room 4 Chair: Prof. Debesh Das |
Session W/D-1: Device Modeling and Simulation Pala-III Chair: Prof. Chandan Sarkar |
Session W/E-1: Sponsored Tutorial Foyer-I Chair: TBD |
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| 10:50-11:10 | W/A-1.1 | System efficiency improvement technique for Automotive Power Management IC using maximum load current selector circuit. | W/B-1.1 | VOP: Architecture of a Processor for Vector Operations in On-line Learning of Neural Networks. | Interactive Presentations I
Click here for Details |
W/D-1.1 | A Novel Capacitorless DRAM Cell Design using Band-gap Engineered Junctionless Double-gate FET. | Controller Concepts for High Density NAND Flash Memories in SSD Applications Erich Haratsch, Seagate |
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| Krishna Kanth Gowri Avalur and Azeemuddin Syed | Gopinath Mahale, Eshan Bhatia, S.K. Nandy, Ranjani Narayan | Dheeraj Kumar Sinha, Amitabh Chatterjee, Vishnuram Abhinav, Gaurav Trivedi, Victor Koldyaev | ||||||||||
| 11:10-11:30 | W/A-1.2 | A Novel Excess Sturdy-MASH-Loop-Delay Compensated Cross-Coupled ΣΔ Modulator. | W/B-1.2 | Software Coherence Management on Non-Coherent Cache Multi-cores. | W/D-1.2 | Write assist scheme to enhance SRAM cell reliability using voltage sensing technique. | ||||||
| Jos Prakash A.V, Babita Roslind Jose, Jimson Mathew | Jian Cai, Aviral Shrivastava | Rajat Gupta, Vijit Gadi, Anirudh Upendar | ||||||||||
| Session W/A-1: Emerging Trends in Digital IC Design Chair: Paritosh Joshi |
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| 11:30-11:50 | W/A-1.3 | E^3R: Energy Efficient Error Recovery for Multi/Triple-Level Cell Non-Volatile Memories. | W/B-1.3 | Partitioned Proportional Round Robin: A Fast and Accurate QoS Aware Scheduler for Embedded Systems. | W/D-1.3 | Analysis and Modeling of Stress over Layer induced Threshold Voltage shift in HKMG nMOS Transistors. | ||||||
| Shivam Swami, Kartik Mohanram | Arnab Sarkar, Arijit Mondal | Apoorva Ojha, Narendra Parihar, Nihar Mohapatra | ||||||||||
| 11:50-12:10 | W/A-1.4 | Reversible Programmable Logic Arrays. | W/B-1.4 | Relaxation Based Circuit Simulation Acceleration over CPU-FPGA. | W/D-1.4 | Unified Model for Sub-Bandgap and Conventional Impact Ionization in RF SOI MOSFETs with Improved Simulator Convergence. | ||||||
| Sajib Kumar Mitra | Vinay B. Y. Kumar, Kulshreshth Dhiman, Mandar Datar, Akash Pacharne, Harihar Narayanan, Sachin Patkar | Chandan Yadav, Anupam Dutta, Saurabh Sirohi, Tamilmani Ethirajan, Yogesh Singh Chauhan | ||||||||||
| 12:10-12:30 | W/A-1.5 | Squaring in Reversible Logic using Zero Garbage and Reduced Ancillary inputs. | W/B-1.5 | Efficient Realization of Table Look-up based Double Precision Floating Point Arithmetic. | W/D-1.5 | Al/HfO2/Si Gate Stack with Improved Physical and Electrical parameters. | User / Designer Track Presentations III [12:20-13:05] |
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| Arindam Banerjee, Debesh Das | Farhad Merchant, Nimash Choudhary, S K Nandy, Ranjani Narayan | Rakesh Vaid, Rakesh Prasher, Devi Dass | W/E-1.2.1 | Bitline Charge Recycling Through Capacitor for Write Cycle of High Density SRAM MemoriesJitesh Poojary, G.S. Visweswaran, Mukul Sarkar and Arun Khamesra | ||||||||
| 12:30-12:50 | W/B-1.6 | Design and Implementation of Blind Assistance System using Real Time Stereo Vision Algorithms. | W/D-1.6 | A Quasi-Static Model for the Coupling Impedance between Coplanar Rectangular Contacts on a Bulk Substrate. | W/E-1.2.2 | Twofold reconfigurable invariant LMS adaptive FIR filter design Padmapriya S and Lakshmi Prabha V | ||||||
| Vaddi Chandra Sekhar, Satyajit Bora, Monalisa Das, Pavan Kumar Manchi, Josephine S and Roy Paily | Anvar A, Gokul R, Akhil C, Shreepad Karmalkar | W/E-1.2.3 | Impact of Design for Manufacturing (DFM) on yield limiting layout configurations on advance technology nodes and their remediesPreet Yadav and Chi-Min Yuan | |||||||||
| 13:00-14:00 | LUNCH Sunderbans |
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| 14:00-14:40 | Plenary Lecture: 2D Crystals for Smart Life Prof. Kaustav Banerjee, University of California Pala Ballroom Chair: Prof. Partha Pratim Das |
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| 14:40-15:20 | Keynote: Everyday Genius: How Design Makes Technology Better Shivananda (Shivoo) R Koteshwar, Director, Design Technology and Wireless Communication Division, MediaTek Pala Ballroom Chair: Prof. Partha Pratim Das |
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| 15:20-15:50 | Tea Break Foyer-II |
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| 15:50-18:00 | Session W/A-2 Pala-I Chair: Prof. Indranil Sengupta |
Session W/B-2: Reliability and Fault Tolerance Pala-II Chair: Prof. Soumyajit Dey |
Session W/C-2 Conference Room 4 Chair: Dr. Pritha Banerjee |
Special Session W/D-2: Technologies for Safe and Intelligent Transportation Systems Pala-III Chair: Prof. Jacob Abraham Co-Chairs: Prof. Samarjit Chakraborty, Dr. S. Ramesh |
Session W/E-2 Foyer-I Chair: TBD |
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| 15:50-16:10 | Embedded Invited Presentation: Hardware/Software Co-Visualization on the Electronic System Level using SystemC Rolf Drechsler et. al. |
W/B-2.1 | Fault Tolerance Through Invariant Checking for Iterative Solvers. | Interactive Presentations II
Click here for Details |
W/D-2.1 | Intelligent Dynamic Toll Pricing for Highway Traffic Congestion Control | User / Designer Track Presentations IV [15:50 -17:05] |
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| Anuradha Annaswamy | W/E-2.1 | Power Integrity Analysis of Networking Chip using Chip Power Model of IP’s: Modelling, Analysis & Solution | ||||||||||
| Felix Loh, Kewal Saluja, Parameswaran Ramanathan | W/D-2.2 | Early Design Space Exploration and Architectural Synthesis for Automotive Embedded Systems | Natish Singla and Amit Kumar Awasthy | |||||||||
| W/E-2.2 | Power Integrity Simulation of High Speed IO | |||||||||||
| 16:10-16:30 | W/B-2.2 | Analysing the Impact of SEUs on SRAM cells with Resistive-Bridge Defects. | Krzysztof Czarnecki | Yagya Dutt Mishra, Mohammad S. Hashmi and Akhilesh Chandra Mishra | ||||||||
| W/D-2.3 | The Challenges of Certification in the Automotive Industry | W/E-2.3 | IP Swap in a Flat Design For Time-to-market | |||||||||
| Sachin Mathur and Anirban Banerjee | ||||||||||||
| Guilherme Medeiros, Leticia Maria Bolzani Poehls, Fabian Luis Vargas, Leticia Maria Bolzani Poehls | Alan Wassyng | W/E-2.4 | Optimal Selection of Spare Flip Flops for Efficient Closure of ECOs in High Performance Designs. | |||||||||
| W/D-2.4 | Architecture for Remote Diagnostics of Automotive Systems | Ayan Datta and Charudhattan Nagarajan | ||||||||||
| W/E-2.5 | Memory Scrambling Checker | |||||||||||
| 16:30-17:30 | Interactive Poster Session | Radhika Gupta, Atul Bhargava and Srisurya Konduri | ||||||||||
| Rahul Mangaram | User / Designer Track Poster Session [17:05-18:00] Click here for Details |
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