VLSID 2015 SPONSORS
| Poster Session 1 (Day 3, January 7, 2015), Session B6, 12:00 - 1:00 P.M |
| P1: Rectilinear Steiner Clock Tree Routing Technique with Buffer Insertion in Presence of Obstacles - Partha Pratim Saha, Sumonto Saha and Tuhina Samanta. |
| P2: Geometric Programming Formulation for Gate-Sizing with Pipelining Constraints - Srinath Naidu. |
| P3: On-the-fly Mapping for Synthesizing Dynamic Domino Circuits - Kadiyala Sai praveen and Samanta Debasis. |
| P4: FirmLeak: A framework for efficient and accurate runtime estimation of leakage power by firmware - Arun Joseph, Anand Haridass, Charles Lefurgy, Spandana Rachamalla, Sreekanth Pai, Diyanesh Chinnakkonda and Vidushi Goyal. |
| P5: Design of 3D antennas for 24 GHz ISM band applications - Putluru Sravani and Madhav Rao. |
| P6: Smart Port Allocation in Adaptive NoC Routers - Reenu James, John Jose and Jobin Antony. |
| P7: EvoDeb: Debugging Evolving Hardware Designs - Debjyoti Bhattacharjee, Ansuman Banerjee and Anupam Chattopadhyay |
| P8: Optimal Test Scheduling of Stacked Circuits Under Various Hardware and Power Constraints - Spencer Millican and Kewal Saluja. |
| P9: A 300KBPS 23.2MHz Binary Frequency Shift Keying Transmitter for USB Power Line Communication in 180nm BiCMOS - Aswin Srinivasa Rao and Karthik Subburaj |
| Poster Session 2 (Day 3, January 7, 2015), Session B7, 2:45 P.M. - 3:45 P.M. |
| P10: A Methodology for Placement of Regular and Structured Circuits - Vikram Singh Saun, Suman Chatterjee and Anand Arunachalam. |
| P11: A Flexible Scalable Hardware Architecture for Radial Basis Function Neural Network -Mahnaz Mohammadi, Nitin Satpute, Rohit Ronge, Jayesh Chandiramani, S K Nandy, Aamir Raihan, Tanmay Verma, Ranjani Narayan and Sukumar Bhattacharya. |
| P12: Sensitivity Analysis Based Predictive Modeling for MPSoC Performance and Energy Estimation - Hongwei Wang, Ziyuan Zhu, Jinglin Shi and Yongtao Su. |
| P13: Accelerating SVM on ultra low power ASIP for high throughput Streaming Applications - Anmol Gupta and Ashutosh Pal. |
| P14: Implementation of NOR Logic based on Material Implication on CMOL FPGA Architecture - Pravin Mane, Nishil Talati, Ameya Riswadkar, Bhavan Jasani and C. K. Ramesha. |
| P15: Analysis of Second-order effect components of drain conductance and its implication on output resistance of wilson current mirror - Kirmender Singh |
| P16: Non-invasive Cuffless Blood Pressure Measurement by Vascular Transit Time - Satya Narayan Shukla, Karan Kakwani, Bipin Kumar Lahkar, Vivek Kumar Gupta, Alwar Jayakrishna, Puneet Vashisht, Induja Sreekanth and Amit Patra. |
| P17: Reliability Enhancement of SoCs Based on Dynamic Memory Access Profiling in Conjunction with PVT Monitoring - Deepak Baranwal, Digvijay Singh, Sidhartha Rout, Soyeb Khanusiya and Sujay Deb. |
| P18: DyMeP: An infrastructure to support Dynamic Memory binding for runtime remaping in CGRAs - Muhammad Adeel Tajammul, Syed M. A. H. Jafri, Peeter Ellervee, Ahmed Hemani, Hannu Tenhunen and Juha Plosila |